GE Delta / Delta-SX  EEPROM documentation

By Dave Karr, KA9FUR

03/02/97 - Initial version, still missing CG information
11/29/00 - Added information on how to calculate CG tones.
01/02/01 - Added information on the reference divider bits as well as
           the notations on the CCT bits.
01/03/01 - Added information on the Delta S firmware with respect to its
           apparant differences to the SX.  Some investigation remains.
06/17/02 - Corrected error regarding bit 0.0
06/07/04 - Added information regarding older Delta-S memory format
         - Clarified some information regarding DCG

-----------------------   Delta-SX Firmware ----------------------------

Based on a CPU which identifies as 0x11 0x01


Memory organisation:

MSB is equal to the binary channel data compliment. Therefore channel
1A resides at memory location Ex, channel 2A resides at memory location
Dx, and so on.

The LSB of the memory location on a per channel basis is:

Receive data
0 -    0.3   0=CG/1=DCG
       0.2   Band control bit W/X*
       0.1   Band control bit Z/Y*
       0.0   CG Bit x
1 -    1.3   N.9
       1.2   R.2
       1.1   R.1
       1.0   R.0
2 -    2.3   N.4
       2.2   N.3
       2.1   N.2
       2.0   N.1
3 -    3.3   N.8
       3.2   N.7
       3.1   N.6
       3.0   N.5
4 -    4.3   A.3
       4.2   A.2
       4.1   A.1
       4.0   A.0
5 -    5.3   N.0
       5.2   1 = No Squelch Tail Eliminator, 0 = STE
       5.1   A.5
       5.0   A.4
6 -    LSN of CG/DCG
7 -    MSN of CG/DCG

6.3, 6.2, 6.1, 6.0, 5.2  CPU cycles
0.0, 7.3, 7.2, 7.1, 7.0  Timer load value

Transmit data
8 -    8.3   0=CG / 1=DCG
       8.2   Band control bit W/X*
       8.1   Band control bit Z/Y*
       8.0   CG Bit x
9 -    9.3   N.9
       9.2   CCT, if set timer value +=2min
       9.1   CCT, if set timer value +=1min
       9.0   CCT, if set timer value +=30sec
A -    A.3   N.4
       A.2   N.3
       A.1   N.2
       A.0   N.1
B -    B.3   N.8
       B.2   N.7
       B.1   N.6
       B.0   N.5
C -    C.3   A.3
       C.2   A.2
       C.1   A.1
       C.0   A.0
D -    D.3   N.0
       D.2   CG lsbit x
       D.1   A.5
       D.0   A.4
E -    LSN of CG/DCG
F -    MSN of CG/DCG

--- Frequency determination ---

Synth  Freq. =  X * N + A   Where X=5000 for 5KHz channel spacing.

For the transmit frequency the calculation is straight forward.  Take the
desired transmit frequency divided by 'X'.  This result is the total channel
divisor.  Next take this result divided by 64.  The integer portion of the
result is 'N'.  Multiplying the fractional result times 64 gives the 'A'
value.

Example:

Desired frequency:   146.34MHz .  Channel divisor is 29268, N=457, A=20

Next convert the decimal numbers to binary and store the bits as indicated
in the table above.

N = 0111001001    A = 010100

This would be stored in channel memory as:

x8  x9  xA  xB  xC  xD
 0   0   4   E   4   9   (This example ignores bits not related to 'N' or 'A')

The receive frequency is computed in exactly the same manner with the
exception that you need to calculate the 1st LO injection frequency instead
of the desired channel frequency.

Example:

For high side injection with a 57.5MHz 1st IF:

Desired frequency:  146.94MHz.  146.94MHz + 57.5MHz = 204.44MHz.
Channel divisor is 40888, N=638 (1001111110), A=56 (111000).



--- Digital Channel Guard ---

Most of the 9 bit DCG codes can be reduced to an equivilant code which has
the MS bit clear, thus reducing it to an 8 bit value.

When the GE software stores values in the EEPROM, the code is generally
reduced to the lowest numeric value, even if the native code value could
have been natively represented as an 8 bit value.

In looking for a pattern as to how GE reduced the codes, I was unable to
come up with hard fast rules.  Given that if a valid code is stored in
the EEPROM in a way that GE's programming software didn't reduce it, their
software is unable to recognize the valid alternative code, even if it is
a natively stored value, and properly present it to the user.  Based on these
observations, I concluded that they must have simply used a lookup table
rather than a programatic approach.

There are a few valid codes which cannot be reduced to an 8 bit value and
those exceptions are handled by way of a lookup table.  The following
lists the relation between stored value, and these eight exceptions:

    Stored Value   DCG Code
    ------------   --------
          3         446
          4         447
          5         452
          6         454
          7         455
          8         462
          9         523
         10         526

For all other codes convert the desired code to its code equivilant using
the tables in LBI31705 or other published lists.  Example:  Code 703 can be
converted to 150.  Load the 8 bit code as:

(octal code)     1   5   0            0   2   3        3   7   1
(binary code)   001 101 000          000 010 011       011 111 001
(hex code)           6    8               1    3            F    9

Store the MSN in location xF and the LSN in xE, where 'x' is the MSN of
the address and is dependant on the channel number.

Bits 8.0 and D.2 are not used in DCG mode.


Also note that for some radios, an inverted DCG code is stored in the EEPROM
even though there is no indication to the user that this is occurring. For
radios that require this, the Niles software will incorrectly read and store
values in the EEPROM.

  

--- Channel Guard ---


Transmit CG tone:


Take the desired tone period divided by 8 (because of the 4 step sine) to
determine the desired clock period.

Example 127.3Hz = 981.932us.

This gets calculated in 2 halves.


0.0 7.3 7.2 7.1 7.0    - This is the hardware timer load value.
 0   1   1   0   0    (12 decimal)

The hardware timer runs at 12.5kHz (80us).  The timer is an up counter and
triggers on an 8 bit rollover.  The value here gets added to 233d and loaded
into the hardware timer.


6.3 6.2 6.1 6.0 5.2
 0   1   1   0   1   (13 decimal)

This value is the delay in CPU machine cycles (2.5us) that is additionally
padded to the overall time value.

Lastly an overhead of 70us is added in the ISR.


Therefore in our example here:

 (23 - 12) * 80uS  + 13 * 2.5us + 70us = 982.5us which yields 127.226Hz


Note:   If 0.0 (or 8.0) is set to zero OR if nibbles 6&7 (or E&F) are both
    zero, then CG is disabled.  0.3 (or 8.3) also needs to be cleared.

------------------------------------
Reference bits R.2, R.1, R.0


R.2 R.1 R.0

 0   0   0    Tx = 4.1666kHz, Rx = 6.25kHz
 0   0   1    4.166kHz   Ref/3168
 0   1   0    5.000kHz   Ref/2640
 0   1   1    6.250kHz   Ref/2112
 1   0   0    3.985kHz   Ref/3312
 1   0   1    4.7826kHz  Ref/2760
 1   1   0    5.97826kHz Ref/2208

 1   1   1    Disables Channel completely

---------------------

If CCT bits (9.2, 9.1, 9.0) are all set to 1's then the transmitter
is disabled for that channel.



-----------------------   Delta-S Firmware ----------------------------

06/07/04 - This section created based on CPU: 19A703241G7, copyright 1983
        This CPU identifies itself as 0x10 0x02


Memory organisation:

MSB is equal to the binary channel data compliment. Therefore channel
1A resides at memory location Ex, channel 2A resides at memory location
Dx, and so on.

The LSB of the memory location on a per channel basis is:

Receive data
0    0.3    1 = Receiver DCG    / 0 = Receiver CG
     0.2    1 = Transmitter DCG / 0 = Transmitter CG
     0.1    1 = STE disabled    / 0 = STE enabled
     0.0   
1 -  1.3   N.9
     1.2   R.2
     1.1   R.1
     1.0   R.0
2 -  2.3   N.4
     2.2   N.3
     2.1   N.2
     2.0   N.1
3 -  3.3   N.8
     3.2   N.7
     3.1   N.6
     3.0   N.5
4 -  4.3   A.3
     4.2   A.2
     4.1   A.1
     4.0   A.0
5 -  5.3   N.0
     5.2   A.6
     5.1   A.5
     5.0   A.4
6 -  LSN of CG/DCG
7 -  MSN of CG/DCG


Nibble 8:

 Bit     3 2 1 0
         -------
         1 0 1 1     CCT = 3 minutes
         0 1 1 1     CCT = 2 minutes
         0 0 1 1     CCT = 1 minute
         0 0 0 0     CCT is disabled

Transmit data
8 - 8.3   CCT 15 += 120 seconds
    8.2   CCT 15 += 60  seconds
    8.1   CCT 15 += 30  seconds
    8.0   CCT 15 += 15  seconds
9 - 9.3   N.9
    9.2  
    9.1  
    9.0  
A - A.3   N.4
    A.2   N.3
    A.1   N.2
    A.0   N.1
B - B.3   N.8
    B.2   N.7
    B.1   N.6
    B.0   N.5
C - C.3   A.3
    C.2   A.2
    C.1   A.1
    C.0   A.0
D - D.3   N.0
    D.2   A.6
    D.1   A.5
    D.0   A.4
E - LSN of CG/DCG
F - MSN of CG/DCG


------------------------------------
Reference bits R.2, R.1, R.0


R.2 R.1 R.0

 0   0   0    Disables Channel

 0   0   1    4.166kHz   Ref/3168
 0   1   0    5.000kHz   Ref/2640
 0   1   1    6.250kHz   Ref/2112
 1   0   0    3.985kHz   Ref/3312
 1   0   1    4.7826kHz  Ref/2760
 1   1   0    5.97826kHz Ref/2208
 1   1   1    3.125kHz   Ref/4224

------------------------------------

Nibbles 6&7, and E&F are CG/DCG information as in the SX firmware except
that the CG tones are based on a lookup table rather than representing
timing values.  The nibble order is still Nibble 7 (and 0xf) representing
the upper nibble.

The DCG method is the same as the SX firmware

The table of tones noted for CG is:

Nibble     7 6
    ---
    0 0    CSQ
    0 1    67.0
    0 2    71.9
    0 3    74.4
    0 4    77.0
    0 5    79.7
    0 6    82.5
    0 7    85.4
    0 8    88.5
    0 9    91.5
    0 A    94.8
    0 B    100.0
    0 C    103.5
    0 D    107.2
    0 E    110.9
    0 F    114.8
    1 0    118.8
    1 1    123.0
    1 2    127.3
    1 3    131.8
    1 4    136.5
    1 5    141.3
    1 6    146.2
    1 7    151.4
    1 8    156.7
    1 9    162.2
    1 A    167.9
    1 B    173.8
    1 C    179.9
    1 D    186.2
    1 E    192.8
    1 F    203.5
    2 0    210.7
    2 1    97.4